The Presentation inside:

Chapter # 5: Arithmetic CircuitsContemporary Logic DesignRandy H. KatzUniversity of California, BerkeleyFall 2000

Motivation Arithmetic circuits are excellent examples of comb. logic design • Time vs. Space Trade-offs Doing things fast requires more logic and thus more space Example: carry lookahead logic • Arithmetic Logic Units Critical component of processor datapath Inner-most "loop" of most computer instructions

Chapter Overview Binary Number Representation Sign & Magnitude, Ones Complement, Twos Complement Binary Addition Full Adder Revisted ALU Design BCD Circuits Combinational Multiplier Circuit Design Case Study: 8 Bit Multiplier

Number Systems Representation of Negative Numbers Representation of positive numbers same in most systems Major differences are in how negative numbers are represented Three major schemes: sign and magnitude ones complement twos complement Assumptions: we'll assume a 4 bit machine word 16 different values can be represented roughly half are positive, half are negative

Number Systems Sign and Magnitude Representation High order bit is sign: 0 = positive (or zero), 1 = negative Three low order bits is the magnitude: 0 (000) thru 7 (111) Number range for n bits = +/-2 -1 Representations for 0 n-1

Number Systems Sign and Magnitude Cumbersome addition/subtraction Must compare magnitudes to determine sign of result Ones Complement N is positive number, then N is its negative 1's complement N = (2 - 1) - N n Example: 1's complement of 7 2 = 10000 -1 = 00001 1111 -7 = 0111 1000 = -7 in 1's comp. Shortcut method: simply compute bit wise complement 0111 -> 1000 4

Number Systems Ones Complement Subtraction implemented by addition & 1's complement Still two representations of 0! This causes some problems Some complexities in addition

Number Representations Twos Complement Only one representation for 0 One more negative number than positive number like 1's comp except shifted one position clockwise

Number Systems Twos Complement Numbers N* = 2 - N n Example: Twos complement of 7 2 = 10000 7 = 0111 1001 = repr. of -7 Example: Twos complement of -7 4 2 = 10000 -7 = 1001 0111 = repr. of 7 4 sub sub Shortcut method: Twos complement = bitwise complement + 1 0111 -> 1000 + 1 -> 1001 (representation of -7) 1001 -> 0110 + 1 -> 0111 (representation of 7)

Number Representations Addition and Subtraction of Numbers Sign and Magnitude 4 + 3 7 0100 0011 0111 -4 + (-3) -7 1100 1011 1111 result sign bit is the same as the operands' sign 4 - 3 1 0100 1011 0001 -4 + 3 -1 1100 0011 1001 when signs differ, operation is subtract, sign of result depends on sign of number with the larger magnitude

Number Systems Addition and Subtraction of Numbers Ones Complement Calculations 4 + 3 7 0100 0011 0111 -4 + (-3) -7 1011 1100 10111 1 1000 4 - 3 1 0100 1100 10000 1 0001 -4 + 3 -1 1011 0011 1110 End around carry End around carry

Number Systems Addition and Subtraction of Binary Numbers Ones Complement Calculations Why does end-around carry work? Its equivalent to subtracting 2 and adding 1 n M - N = M + N = M + (2 - 1 - N) = (M - N) + 2 - 1 n n (M > N) -M + (-N) = M + N = (2 - M - 1) + (2 - N - 1) = 2 + [2 - 1 - (M + N)] - 1 n n n n M + N < 2 n-1 after end around carry: = 2 - 1 - (M + N) n this is the correct form for representing -(M + N) in 1's comp!

Number Systems Addition and Subtraction of Binary Numbers Twos Complement Calculations 4 + 3 7 0100 0011 0111 -4 + (-3) -7 1100 1101 11001 4 - 3 1 0100 1101 10001 -4 + 3 -1 1100 0011 1111 If carry-in to sign = carry-out then ignore carry if carry-in differs from carry-out then overflow Simpler addition scheme makes twos complement the most common choice for integer number systems within digital systems

Number Systems Addition and Subtraction of Binary Numbers Twos Complement Calculations Why can the carry-out be ignored? -M + N when N > M: M* + N = (2 - M) + N = 2 + (N - M) n n Ignoring carry-out is just like subtracting 2 n -M + -N where N + M < or = 2 n-1 -M + (-N) = M* + N* = (2 - M) + (2 - N) = 2 - (M + N) + 2 n n After ignoring the carry, this is just the right twos compl. representation for -(M + N)! n n

Number Systems Overflow Conditions Add two positive numbers to get a negative number or two negative numbers to get a positive number 5 + 3 = -9 -7 - 2 = +7 0000 0001 0010 0011 1000 0101 0110 0100 1001 1010 1011 1100 1101 0111 1110 1111 +0 +1 +2 +3 +4 +5 +6 +7 -8 -7 -6 -5 -4 -3 -2 -1 0000 0001 0010 0011 1000 0101 0110 0100 1001 1010 1011 1100 1101 0111 1110 1111 +0 +1 +2 +3 +4 +5 +6 +7 -8 -7 -6 -5 -4 -3 -2 -1

Number Systems Overflow Conditions 5 3 -8 0 1 1 1 0 1 0 1 0 0 1 1 1 0 0 0 -7 -2 7 1 0 0 0 1 0 0 1 1 1 0 0 1 0 1 1 1 5 2 7 0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 1 -3 -5 -8 1 1 1 1 1 1 0 1 1 0 1 1 1 1 0 0 0 Overflow Overflow No overflow No overflow Overflow when carry in to sign does not equal carry out

Networks for Binary Addition Half Adder With twos complement numbers, addition is sufficient Half-adder Schematic

Networks for Binary Addition Full Adder Cascaded Multi-bit Adder usually interested in adding more than two bits this motivates the need for the full adder

Networks for Binary Addition Full Adder S = CI xor A xor B CO = B CI + A CI + A B = CI (A + B) + A B

Networks for Binary Addition Full Adder/Half Adder Alternative Implementation: 5 Gates A B + CI (A xor B) = A B + B CI + A CI Standard Approach: 6 Gates +

Networks for Binary Addition Adder/Subtractor A - B = A + (-B) = A + B + 1

Networks for Binary Addition Carry Lookahead Circuits Critical delay: the propagation of carry from low to high order stages late arriving signal two gate delays to compute CO 4 stage adder final sum and carry

Networks for Binary Addition Carry Lookahead Circuits Critical delay: the propagation of carry from low to high order stages 1111 + 0001 worst case addition T0: Inputs to the adder are valid T2: Stage 0 carry out (C1) T4: Stage 1 carry out (C2) T6: Stage 2 carry out (C3) T8: Stage 3 carry out (C4) 2 delays to compute sum but last carry not ready until 6 delays later

Networks for Binary Addition Carry Lookahead Logic Carry Generate Gi = Ai Bi must generate carry when A = B = 1 Carry Propagate Pi = Ai xor Bi carry in will equal carry out here Si = Ai xor Bi xor Ci = Pi xor Ci Ci+1 = Ai Bi + Ai Ci + Bi Ci = Ai Bi + Ci (Ai + Bi) = Ai Bi + Ci (Ai xor Bi) = Gi + Ci Pi Sum and Carry can be reexpressed in terms of generate/propagate:

Networks for Binary Addition Carry Lookahead Logic Reexpress the carry logic as follows: C1 = G0 + P0 C0 C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 C0 C3 = G2 + P2 C2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0 C4 = G3 + P3 C3 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0 Each of the carry equations can be implemented in a two-level logic network Variables are the adder inputs and carry in to stage 0!

Networks for Binary Addition Carry Lookahead Implementation Adder with Propagate and Generate Outputs Increasingly complex logic

Networks for Binary Addition Carry Lookahead Logic Cascaded Carry Lookahead Carry lookahead logic generates individual carries sums computed much faster

Networks for Binary Addition Carry Lookahead Logic Cascaded Carry Lookahead 4 bit adders with internal carry lookahead second level carry lookahead unit, extends lookahead to 16 bits

Networks for Binary Addition Carry Select Adder Redundant hardware to make carry calculation go faster compute the high order sums in parallel one addition assumes carry in = 0 the other assumes carry in = 1

Arithmetic Logic Unit Design Sample ALU Logical and Arithmetic Operations Not all operations appear useful, but "fall out" of internal logic

Arithmetic Logic Unit Design Sample ALU Traditional Design Approach Truth Table & Espresso 23 product terms! Equivalent to 25 gates .i 6 .o 2 .ilb m s1 s0 ci ai bi .ob fi co .p 23 111101 10 110111 10 1-0100 10 1-1110 10 10010- 10 10111- 10 -10001 10 010-01 10 -11011 10 011-11 10 --1000 10 0-1-00 10 --0010 10 0-0-10 10 -0100- 10 001-0- 10 -0001- 10 000-1- 10 -1-1-1 01 --1-01 01 --0-11 01 --110- 01 --011- 01 .e

Arithmetic Logic Unit Design Sample ALU Multilevel Implementation .model alu.espresso .inputs m s1 s0 ci ai bi .outputs fi co .names m ci co [30] [33] [35] fi 110--- 1 -1-11- 1 --01-1 1 --00-0 1 .names m ci [30] [33] co -1-1 1 --11 1 111- 1 .names s0 ai [30] 01 1 10 1 .names m s1 bi [33] 111 1 .names s1 bi [35] 0- 1 -0 1 .end 12 Gates

Arithmetic Logic Unit Design Clever Multi-level Logic Implementation Sample ALU 8 Gates (but 3 are XOR) S1 = 0 blocks Bi Happens when operations involve Ai only Same is true for Ci when M = 0 Addition happens when M = 1 Bi, Ci to Xor gates X2, X3 S0 = 0, X1 passes A S0 = 1, X1 passes A Arithmetic Mode: Or gate inputs are Ai Ci and Bi (Ai xor Ci) Logic Mode: Cascaded XORs form output from Ai and Bi

Arithmetic Logic Unit Design 74181 TTL ALU

Arithmetic Logic Unit Design 74181 TTL ALU Note that the sense of the carry in and out are OPPOSITE from the input bits Fortunately, carry lookahead generator maintains the correct sense of the signals

Arithmetic Logic Unit Design 16-bit ALU with Carry Lookahead

BCD Addition BCD Number Representation Decimal digits 0 thru 9 represented as 0000 thru 1001 in binary Addition: 5 = 0101 3 = 0011 1000 = 8 5 = 0101 8 = 1000 1101 = 13! Problem when digit sum exceeds 9 Solution: add 6 (0110) if sum exceeds 9! 5 = 0101 8 = 1000 1101 6 = 0110 1 0011 = 1 3 in BCD 9 = 1001 7 = 0111 1 0000 = 16 in binary 6 = 0110 1 0110 = 1 6 in BCD

BCD Addition Adder Design Add 0110 to sum whenever it exceeds 1001 (11XX or 1X1X)

Combinational Multiplier Basic Concept multiplicand multiplier 1101 (13) 1011 (11) 1101 1101 0000 1101 * 10001111 (143) Partial products product of 2 4-bit numbers is an 8-bit number

Combinational Multiplier Partial Product Accumulation A0 B0 A0 B0 A1 B1 A1 B0 A0 B1 A2 B2 A2 B0 A1 B1 A0 B2 A3 B3 A2 B0 A2 B1 A1 B2 A0 B3 A3 B1 A2 B2 A1 B3 A3 B2 A2 B3 A3 B3 S6 S5 S4 S3 S2 S1 S0 S7

Combinational Multiplier Partial Product Accumulation Note use of parallel carry-outs to form higher order sums 12 Adders, if full adders, this is 6 gates each = 72 gates 16 gates form the partial products total = 88 gates!

Combinational Multiplier Another Representation of the Circuit Building block: full adder + and 4 x 4 array of building blocks

Case Study: 8 x 8 Multiplier TTL Multipliers Two chip implementation of 4 x 4 multipler

Case Study: 8 x 8 Multiplier Problem Decomposition How to implement 8 x 8 multiply in terms of 4 x 4 multiplies? A7-4 B7-4 A3-0 B3-0 * A3-0 * B3-0 A7-4 * B3-0 A3-0 * B7-4 A7-4 * B7-4 = PP0 = PP1 = PP2 = PP3 P15-12 P11-8 P7-4 P3-0 8 bit products P3-0 = PP0 P7-4 = PP0 + PP1 + PP2 P11-8 = PP1 + PP2 + PP3 P15-12 = PP3 3-0 3-0 3-0 3-0 7-4 7-4 3-0 7-4 + Carry-in + Carry-in + Carry-in

Case Study: 8 x 8 Multiplier Calculation of Partial Products Use 4 74284/285 pairs to create the 4 partial products

Case Study: 8 x 8 Multiplier Three-At-A-Time Adder Clever use of the Carry Inputs Sum A[3-0], B[3-0], C[3-0]: Two Level Full Adder Circuit Note: Carry lookahead schemes also possible!

Case Study: 8 x 8 Multiplier Three-At-A-Time Adder with TTL Components Full Adders (2 per package) Standard ALU configured as 4-bit cascaded adder (with internal carry lookahead) Note the off-set in the outputs

Case Study: 8 x 8 Multiplier Accumulation of Partial Products Just a case of cascaded three-at-a-time adders!

Case Study: 8 x 8 Multiplier The Complete System

Case Study: 8 x 8 Multiplier Package Count and Performance 4 74284/74285 pairs = 8 packages 4 74183, 3 74181, 1 74182 = 8 packages 16 packages total Partial product calculation (74284/285) = 40 ns typ, 60 ns max Intermediate sums (74183) = 9 ns/20ns = 15 ns average, 33 ns max Second stage sums w/carry lookahead 74LS181: carry G and P = 20 ns typ, 30 ns max 74182: second level carries = 13 ns typ, 22 ns max 74LS181: formations of sums = 15 ns typ, 26 ns max 103 ns typ, 171 ns max

Chapter Review We have covered: • Binary Number Representation positive numbers the same difference is in how negative numbers are represented twos complement easiest to handle: one representation for zero, slightly complicated complementation, simple addition • Binary Networks for Additions basic HA, FA carry lookahead logic • ALU Design specification and implementation • BCD Adders Simple extension of binary adders • Multipliers 4 x 4 multiplier: partial product accumulation extension to 8 x 8 case

×

HTML:

Ссылка:

Or sign in using your account

Do you have the account? Create account